View EL4089_462441.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
EL4089
Data Sheet July 1998, Rev C FN7158
DC Restored Video Amplifier
The EL4089 is an 8-pin complete DCrestored monolithic video amplifier sub-system. It contains a high quality video amplifier and a nulling, sample-and-hold amplifier specifically designed to stabilize video performance. When the HOLD logic input is set to a TTL/CMOS logic 0, the sample - and - hold amplifier can be used to null the DC offset of the video amplifier. When the HOLD input goes to a TTL/CMOS logic l, the correcting voltage is stored on the video amplifier's input coupling capacitor. The correction voltage can be further corrected as need be, on each video line. The video amplifier is optimized for video performance and low power. Its current feedback design allows the user to maintain essentially the same bandwidth over a gain range of nearly 10:1. The amplifier drives back-terminated 75 lines. The EL4089 is fabricated in Elantec's proprietary Complementary Bipolar process which produces NPN and PNP transistors with equivalent AC and DC performance. The EL4089 is specified for operation over -40C to +85C temperature range.
Features
* Complete video level restoration system * 0.02% differential gain and 0.05 differential phase accuracy at NTSC * 60MHz bandwidth * 0.1dB flatness to 10MHz * VS = 5V to 15V * TTL/CMOS hold signal
Applications
* Input amplifier in video equipment * Restoration amplifier in video mixers
Ordering Information
PART NUMBER EL4089CN EL4089CS TEMP. RANGE -40C to +85C -40C to +85C PACKAGE 8-Pin PDIP 8-Pin SO PKG. NO. MDP0031 MDP0027
Pinout
EL4089 (8-PIN PDIP, SO) TOP VIEW
DC Restoring Amplifier with a gain of 2, restoring to ground
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL4089
Absolute Maximum Ratings (TA = 25C)
Voltage between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V
Voltage between VIN+, S/HIN+,and GND pins . . (V+) +0.5V to (V-) -0.5V
VOUT Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Current into VIN- and HOLD Pins . . . . . . . . . . . . . . . . . . . . . . . 5mA
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature Plastic DIP or SOL. . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Open-Loop DC Electrical Specifications
PARAMETER AMPLIFIER SECTION (HOLD = 5V) VOS Ib+ IbROL RINCMRR VO ISC RESTORE SECTION VOS, Comp Ib+, r IOUT CMRR PSRR VTHRESHOLD IIH, Hold IIL, Hold SUPPLY CURRENT Isy, Hold Isy, Sampling NOTES: 1. For current feedback amplifiers, AVOL = ROL/RIN-. 2. VCM = 10V for VS = 15V. Supply Current (HOLD = 5V) Supply Current (HOLD = 0V) Input Offset Voltage IN+ Input Bias Current IN- Input Bias Current Transimpedance (Note 1) IN- Resistance
Provisional Supplies at 15V, Load = 1k; TA = +25C TEMP MIN TYP MAX UNITS
DESCRIPTION
+25C +25C +25C +25C +25C +25C +25C +25C 44 12 45 180
12 1 18 800 20 60 13 100
25 5 150
mV A A k dB V mA
Common Mode Rejection Ratio (Note 2) Output Voltage Swing Short Circuit Current (IN+ Only Driven to 0.5V)
Composite Input Offset Voltage (Note 3) Restore In+ Input Bias Current Restoring Current Available Common Mode Rejection Ratio (Note 2) Power Supply Rejection Ratio (Note 4) HOLD Logic Threshold HOLD Input Current @ Logic High HOLD Input Current @ Logic Low
+25C +25C +25C +25C +25C +25C +25C +25C 180 60 60 0.8
3 3 300 70 90
7 12
mV A A dB dB
2.0 1 5 5 15
V A A
+25C +25C
4.8 5.0
6.0 6.5
9.0 11.0
mA mA
3. Measured from S/H Input to amplifier output, while restoring. 4. VOS is measured at VS = 4.5V and VS = 16V, both supplies are changed simultaneously.
2
EL4089
Closed-Loop AC Electrical Specifications
PARAMETER AMPLIFIER SECTION SR SR BW Slew Rate (Note 2) Slew Rate with 5V Supplies (Note 2) Bandwidth 5V Supplies -3dB -3dB BW Bandwidth 5V Supplies 0.1dB 0.1dB dG Differential Gain at 3.58MHz (Note 3) VS = 15V VS = 5V dPh Differential Phase at 3.58MHz (Note 3) VS = 15V VS = 5V RESTORE SECTION SR THE THD NOTES: 1. Test fixture was designed to minimize capacitance at the IN- input. A "good" fixture should have less than 2pF of stray capacitance to ground at this very sensitive pin. See application notes for further details. 2. SR measured at 20% to 80% of a 4VPK-PK square wave. 3. DC offset from -0.714V through +0.714V, ac amplitude is 286mVP-P, equivalent to 40 IRE. Restore Amplifier Slew Rate (Test Circuit) 20%--80% Time to Enable Hold Time to Disable Hold 25 25 40 V/s ns ns 500 275 60 55 25 23 0.02 0.03 0.05 0.06 V/s V/s MHz MHz MHz MHz % % Provisional Supplies at 15V, Load = 150 and 15pF. RF and RG = 300; AV = 2, TA = 25C. (Note 1) DESCRIPTION MIN TYP MAX UNITS
3
EL4089 Typical Performance Curves
Supply Current vs Temperature VS = 15V Supply Current vs Supply Voltage
Restoring Current vs Temperature
Amplifier Input Current vs Die Temperature
Amplifier Output Voltage vs Die Temperature; VS = 15V
Amplifier Offset Voltage vs Die Temperature
4
EL4089 Typical Performance Curves
(Continued)
Transimpedance (ROL) vs Die Temperature
CMRR for Amplifier and Restore Section vs Die Temperature
Relative Frequency Response for Various Gains, RF = 300
Frequency Response vs Supply AV = 2; RF = 300
Frequency Response Flatness vs Supply AV = 2; RF = 300
Frequency Response Flatness for Various Load and Supply Conditions AV = 2; RF = 300
5
EL4089 Typical Performance Curves
(Continued)
Differential Gain vs DC Input Offset; AV = 2, FO = 3.58MHz, RL = 150
Frequency Response Flatness vs CIN-; AV = 2; RF = 300
Differential Phase vs DC Input Offset; AV = 2; FO = 3.58MHz; RL = 150
8-Pin Plastic DIP Maximum Power Dissipation vs Ambient Temperature
8-Lead SO Maximum Power Dissipation vs Ambient Temperature
Typical Application
The EL4089 can be used to DC-restore a video waveform (see Figure 1). The circuit forces the cable driving video amplifier's output to ground when the HOLD pin is at a logic low. The "correction voltage" is stored on capacitor CX1, an external ceramic capacitor. The capacitor value is chosen from the system requirements. The typical input bias current to the video amplifier is 1A, so for a 62s hold time, and a
0.01F capacitor, the output voltage drift is 6.2mV in one line. The S/H amplifier can provide a typical current of 300A to charge capacitor CX1, so with a 1.2s sampling time, the output can be corrected by 36mV in each line. Using a smaller value of CX1 increases both the voltage that can be corrected, and the drift while being held, likewise, using a larger value of CX1, reduces the voltages. The RX1 resistor is in the circuit purely to simulate some external source impedance, and is not needed as a real
6
EL4089
component. Likewise for RX2. The 75 back terminating resistor RXT is recommended when driving 75 cables. The board layout should have a ground plane underneath the EL4089, with the ground plane cut away from the vicinity of the VIN- pin, (pin 1). This helps to minimize the stray capacitance on pin 1. Power supply bypassing is important, and a 0.1F ceramic capacitor, from each power pin to ground, placed very close to the power pins, together with a 4.7F tantalum bead capacitor, is recommended. When both digital and analog grounds are on the same board, the EL4089 should be on the analog ground. The digital ground can be connected to the Analog ground through a 100-300 resistor, near the EL4089. This allows the digital signal a return path, while preventing the digital noise from corrupting the analog ground.
TABLE OF CHARGE STORAGE CAPACITOR VS DROOP CHARGING RATES (NOTE) CAP VALUE nF 10 33 100 DROOP IN 60s mV 6 1.8 0.6 CHARGE IN 1.2s mV 36 11 3.6 CHARGE IN 4s mV 120 36 12
The S/H amplifier is current output and causes a small load on the input source during sampling. When sampling is done on the back porch with color burst there will be a small load on the color burst. Therefore for best performance, the input should be driven from an amplifier output or a 75 cable with 75 termination.
NOTE: Basic formulae are: V (droop) = Ib+ * (Line time - Sample time) / Capacitor and V (charge) = IOUT * Sample time / Capacitor
For best results the source impedance should be kept low, using a buffer for example.
FIGURE 1.
7
EL4089 EL4089 Macromodel
* Connections: VIN* | VIN+ * | | Ref * | || Hold * | || | -Vsupply * | || | | VOUT * | || | | | +Vsupply * | || |||| .subckt EL4089/EL 1 2 3 4 6 7 8 ******** Restore section g10 2 0 xx 0 430u e10 yy 0 WW 3 4.66 Rfl 7 ww 8K Cfl ww 0 20p Rd yy ss 100 d10 xx 0 dd d20 0 xx dd s1 xx ss 4 0 swno s2 0 xx 4 0 swnc rsl 3 0 999K Rhh 4 0 100K .model swno vswitch (von=0.8 voff=2.4) .model swnc vswitch (von=2.4 voff=0.8) ********************** * Input Stage e1 10 0 2 0 1.0 vis 10 9 0V h2 9 12 Vxx 1.0 r1 1 11 20 I1 11 12 20nH iinp 2 0 1u iinn 1 0 18u r12 2 0 2MEG * Slew Rate Limiting H1 13 0 vis 600 r2 13 14 1k d1 14 0 dd d2 0 14 dd * High Frequency Pole e2 30 0 14 0 0.00166666666 I3 30 17 1.47u c5 17 0 0.47p r5 17 0 700 * Transimpedance Stage g1 0 18 17 0 1.0 rol 18 0 800k cdp 18 0 11p * Output Stage q1 6 18 19 qp q2 8 18 20 qn q3 8 19 21 qn q4 6 29=0 22 qp r7 21 7 3 r8 22 7 3 ios1 8 19 2mA iso2 20 6 2mA *Supply Current ips 8 6 6.5mA *Error Term
8
EL4089
iovs 0 23 12m Vxx 23 0 0V e4 24 0 2 0 1.0 e5 25 0 8 0 1.0 e6 26 0 6 0 1.0 r9 23 24 560 r10 25 23 1k r11 26 23 1k * Models .model qn npn (is=5e-15, bf=100, tf=0.1ns) .model qp pnp (is=5e-15, bf=100, tf=0.1ns) .model dclamp d(is=1e-20, ibv=0.266, bv=2.24, n=4)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9

▲Up To Search▲

Price & Availability of EL4089

	To Download EL4089 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .